readme
I'm a B.Tech Electrical & Computer Engineering student at Shiv Nadar University (2024–2028). My research is FPGA acceleration of neural networks with Prof. Amit Acharyya's group at IIT Hyderabad, supervised by Dr. Rakesh Palisetty. I take a CNN from training through HLS and quantization to a custom IP on a Xilinx ZCU104, then benchmark it on the board.
Outside the lab I build the hardware I use every day: a multi-host BLE macropad with its own companion app, and active studio speakers whose crossover is code instead of copper.
The little face following you around this site lives on that macropad's screen. It's the same expression table and spring physics as the firmware, running in your browser.
more on the bench
Self-hosted Claper in place of a paid tool. Sized for about 250 attendees, it peaked at 89 concurrent and recorded 420 votes across 5 polls. When campus Wi-Fi client isolation blocked LAN hosting, I moved it behind a Cloudflare tunnel with TLS.
Local retrieval over 14 project repositories (952 chunks) behind a redacting mirror. A 20-question eval guided the embedder and indexing changes that took hit@8 from 8/14 to 19/20. The remaining misses traced to stale source documents, not retrieval.
120° six-step PWM with Hall-sensor commutation and a closed speed loop. MATLAB Function blocks that would not deploy to the DS1103 were recast as look-up tables and plain arithmetic.
A five-joint arm that mirrors a hand-held puppet replica: the puppet's joint angles are read and replayed on the servos through a PCA9685 driver.
A Flask / SQLite component-inventory app, and a Linux NAS media server published through a rate-limited Cloudflare tunnel.
spectrum
Each lit segment is one project on this site that uses tools from that area. No self-rated percentages.
timing diagram
May – Jul 2026 · Hyderabad
IIT Hyderabad
End-to-end CNN inference on a ZCU104; a matched-twin hls4ml vs. Vitis AI comparison across three pipelines; a custom AXI-DMA streaming IP at 33,497 inf/s, 3.1× the DPU in a matched session.
Summer 2025 · Hyderabad
IIT Hyderabad
Trained VGG16, ResNet50 and MobileNet on CIFAR-100 to about 89% accuracy; designed and evaluated custom pooling layers.
2024 – present
Shiv Nadar University, with IIT Hyderabad · supervisor Dr. Rakesh Palisetty
I lead the FPGA ML deployment study with Prof. Amit Acharyya's group. It began on an RFSoC 4x2 and moved to the ZCU104 so both toolchains build reproducibly on the free Vivado tier.
2024 – 2028 · Greater Noida
Shiv Nadar University
in preparation
a journal article and a letter
open a connection
I'm open to research collaborations, internships and interesting hardware problems, especially FPGA / ASIC design, edge AI hardware, embedded systems and audio DSP.